A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

Total ionizing dose effect in an input/output device for flash memory

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.     

工程开挖的结构效应与防治对策──以兰州西郊滑坡为例

开挖引起的滑坡作用不仅取决于斜坡带本身的地质结构,更取决于工程开挖与斜坡地质结构相互作用,因此科学地工程开挖可以避免这类地质灾害的发生。本文以2001年7月1日发生在兰州西郊白垩系砂岩顺层山坡上天然气长输管道管沟深开挖引起的岩层滑动和由此造成的兰州市煤气管道大变形问题为例,揭示了层间剪切带的工程开挖效应和对边坡稳定性的控制作用,总结了此类地质灾害教训。     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

减小高速列车荷载对地面结构损害的数值分析

用数值模拟的方法研究无填充壕沟、注水壕沟和砼填充壕沟对地表高速列车荷载引起振动的防护能力。运用LS-DYNA软件,对高速列车荷载作用下地面结构所产生的动力响应进行数值分析。通过数值模拟计算发现,无填充壕沟和注水壕沟可以明显降低地面结构关键点上的加速度与应力幅值,而砼填充壕沟并无明显降低结构中关键点上的加速度与应力值。对于地表高速列车荷载引起的地面结构振动,无填充壕沟与注水壕沟都有明显的防护作用,而砼填充壕沟的防护作用不明显。     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

The repetitive unclamped inductive switching (UIS) avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO₂ interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.     

Improvement on short-circuit ability of SiC super-junction MOSFET with partially widened pillar structure

A novel 1200 V SiC super-junction (SJ) MOSFET with a partially widened pillar structure is proposed and investigated by using the two-dimensional numerical simulation tool. Based on the SiC SJ MOSFET structure, a partially widened P-region is added at the SJ pillar region to improve the short-circuit (SC) ability. After investigating the position and doping concentration of the widened P-region, an optimal structure is determined. From the simulation results, the SC withstand times (SCWTs) of the conventional trench MOSFET (CT-MOSFET), the SJ MOSFET, and the proposed structure at 800 V DC bus voltage are 15 μs, 17 μs, and 24 μs, respectively. The SCWTs of the proposed structure are increased by 60% and 41.2% in comparison with that of the other two structures. The main reason for the proposed structure with an enhanced SC capability is related to the effective suppression of saturation current at the high DC bias conditions by using a modulated P-pillar region. Meanwhile, a good Baliga's FOM ($BV^{2}/R_{\rm on}$) also can be achieved in the proposed structure due to the advantage of the SJ structure. In addition, the fabrication technology of the proposed structure is compatible with the standard epitaxy growth method used in the SJ MOSFET. As a result, the SJ structure with this feasible optimization skill presents an effect on improving the SC reliability of the SiC SJ MOSFET without the degeneration of the Baliga's FOM.     

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench(HK TG VDMOS) is proposed in this paper.The HK TG VDMOS features a high-k(HK) trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage(BV).Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction(SJ) vertical double-diffused metal-oxide semiconductor(VDMOS),the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS(TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).